`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2021/08/05 11:53:30
// Design Name: 
// Module Name: FeatureInBuffer
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module FeatureInBuffer
#(parameter ADDR_WIDTH = 32,
  parameter DATA_WIDTH = 32,
  parameter BANK = 4,
  parameter DEPTH = 1024)
(
input logic clk,
input logic rst,
//write input data
input logic [ADDR_WIDTH-1:0] wr_addr,
input logic [DATA_WIDTH-1:0] wr_data,
input logic we,
//read multi data
input logic [ADDR_WIDTH-1:0] rd_addr,
output logic [DATA_WIDTH-1:0] rd_data [0:BANK-1]
    );
logic wen [0:BANK-1];
logic [ADDR_WIDTH-1:0] write_addr;
logic [DATA_WIDTH-1:0] write_data;
//
always_ff@(posedge clk)
    write_data<=wr_data;
//写数据，单端口写,bank=4的情形
always_ff@(posedge clk,posedge rst)
if(rst)
for(int i=0;i<BANK;i++)
    wen[i]<=0;
else if(we)
begin
    for(int i=0;i<BANK;i++)
        wen[i]<=0;
    if(wr_addr<DEPTH)               //写BANK0
    begin
        wen[0]<=1;
        write_addr<=wr_addr;
    end
    else if(wr_addr<2*DEPTH)
    begin
        wen[1]<=1;
        write_addr<=wr_addr-DEPTH;
    end
    else if(wr_addr<3*DEPTH)
    begin
        wen[2]<=1;
        write_addr<=wr_addr-2*DEPTH;
    end
    else
    begin
        wen[3]<=1;
        write_addr<=wr_addr-3*DEPTH;
    end
end
else
begin
    for(int i=0;i<BANK;i++)
        wen[i]<=0; 
end

//
genvar i;
generate
    for(i=0; i<BANK; i++)
    begin: bram_inst
        BlockRAM 
        #(.ADDR_WIDTH(ADDR_WIDTH),
          .DATA_WIDTH(DATA_WIDTH),
          .DEPTH(DEPTH))
        U (
        .clk(clk),
        .rst(rst),
        //read port
        .rd_addr(rd_addr),
        .rd_data(rd_data[i]),
        //write port
        .we(wen[i]),
        .wr_addr(write_addr),
        .wr_data(write_data)
        );
    end
endgenerate
endmodule
